A known FET switching arrangement comprises two FETs connected source-to-source and gate-to-gate, each FET having a substrate or bulk region which is connected to its source. A biasing impedance is connected between the gates and sources of the FETs. The FETs are turned on by drawing bias current through the biasing impedance to develop a voltage between the gates and sources of the FETs which exceeds the threshold voltage of the FETs. When the FETs are turned on, the arrangement can pass current through the two FETs in series in either of two opposite directions. In the absence of such bias current, the biasing impedance ensures that the FETs are off, so that the arrangement blocks current in both of the two opposite directions.
When the FETs are turned on, and current is passed through the FETs in series, a pn junction defined by the drain and substrate or bulk region of one of the FETs is forward biased. The forward bias is the product of the current passed by the FETs and the on-impedance of the FETs. If this product is too large, the forward biased pn junction can inject enough carriers into the substrate or bulk region to cause undesired latching.
To avoid this problem, the FETs must be made large enough to ensure that their on-impedance will not develop sufficient voltage to turn on the pn junction at the maximum current to be passed by the switching arrangement. For many applications, the FETs must be made so large that, where the switching arrangement is part of a monolithic integrated circuit, its area has a significant impact on the total size and therefore the cost of the integrated circuit. A FET switching arrangement which permits the use of smaller FETs for most applications would therefore be desirable.
Another known FET switching arrangement combines a diode bridge with a single FET. The diode bridge is used to ensure that current flows in the same direction through the FET when the FET is on, regardless of the direction of current flow between external terminals of the switching arrangement. The direction of current flow through the FET is arranged to ensure that the pn junction defined by the drain and the substrate or bulk region is never forward biased, so that latching is not a problem.
Unfortunately, the diode bridge is required to withstand the full voltage applied to the switching arrangement without passing current when the FET is off. High voltage diodes are needed to meet this requirement, and such high voltage diodes are not available in many of the semiconductor technologies in which FET switching arrangements may be implemented.
In some FET circuits, the problem of undesired carrier injection into the substrate or bulk region of the FETs is avoided by applying an appropriate DC bias to the substrate or bulk region to ensure that the pn junctions through which such injection could occur are never forward biased. The DC bias applied to the substrate or bulk region is referenced to fixed supply voltages which power the FET circuits.
Unfortunately, this approach is not readily applicable to FET switching arrangements which do not have fixed supply voltages limiting the range of voltages applied to the FETs.